instruction execution

英 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

美 [ɪnˈstrʌkʃn ˌeksɪˈkjuːʃn]

网络  指令执行

计算机

英英释义

noun

• (computer science) the process of carrying out an instruction by a computer
  Synonym:execution

双语例句

• If supervision engineer issued a directive, contractor should change by supervision engineer change instruction execution.
  若监理工程师发出了变更指令，承包人就应按监理工程师的变更指令执行。
• Compile the assembler into machine code so that generate PLE file in order to implement the execution mechanism of PLC virtual machine. In this way, the instruction execution speed of PLC is greatly increased and we can save much memory.
  用汇编编译器编译转变成功的汇编程序产生机器码，从而构造出可执行文件&PLE文件，实现PLC虚拟机的机器码执行机制，这样大大提高了PLC指令的执行速度，同时大大节约了内存空间。
• But in reality, the upper software drives the underlying hardware, for example different instruction execution and data access affect the underlying hardware circuit directly and result in different power generation.
  但在实际情况中，底层硬件受上层软件驱动，例如不同指令执行和数据存取等软件指令直接影响底层硬件的电路活动，导致不同功耗产生。
• The Digital Signal Processing which is regarded as CPU on board has some advantages, such as fast instruction execution, high bus bandwidth, and high speed real-time data processing.
  数据采集卡部分使用使用DSP来作采集卡CPU具有指令执行速度快、总线带宽高、可以完成数据的高速实时处理等优点。
• The article essentially describes such points as instruction execution and memory management in constructing a virtual running embedded system.
  文中着重介绍了构建嵌入式虚拟运行平台中的指令执行、存储器管理等核心技术问题。
• This thesis sets forth case instruction in terms of executive condition, organizing execution and realistic meaning and so on.
  文中从案例教学法的实施条件、组织实施过程、现实意义等方面进行了阐述。
• It is more efficient to design a simple instruction set that enable the execution of one instruction per clock cycle.
  设计一个能够在一个时钟周期执行一条指令的简单指令系统才是更有效的。
• This paper has discussed the relationship between the machine cycle and instruction execution time for superscalar RISC architecture, issuing multiple instructions in one machine cycle. Several new design features of superscalar RISC architecture with single execution unit and multiple function units have been analysed.
  本文讨论超标量RISC结构中单周期发多条指令中周期和执行指令时间的相对关系，并分析了新型超标量RISC结构的实现方案，其中包括具有单个执行部件和多个执行部件的结构。
• A4-stage instruction pipeline for instruction execution makes at-speed test possible.
  四级指令流水线的引入使全速测试成为可能。
• As the core of SOC, CPU ′ s performance is mostly determined by instruction ′ s execution efficiency. Pipeline increases the instruction ′ s execution pace and improves the CPU ′ s performance.
  作为SOC的核心，CPU的性能主要取决于指令的执行效率，而采用流水线方式大大增加了指令的执行速度，提高了CPU的性能。